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Highly Reliable Storage

The notion of storing critical data on RAM and Flash chips evokes understandable concern with data center and application administrators. Images of crashing desktops losing all the data stored in memory lead current and prospective customers to ask Texas Memory Systems what it does to protect the critical data stored on its products.
As an engineering-centered company, Texas Memory Systems has responded to these concerns with exclusive and unique features for its solid state disk and cache systems. After nearly 30 years, TMS has evolved a line of storage that is by far the most reliable and feature-rich in the industry.

Battery Backup

Texas Memory Systems solid state disks are non-volatile systems. Just like conventional RAID devices, they maintain their data when power is shutdown or unexpectedly lost. With our RAM SSDs, all reads and writes occur on RAM chips for maximum performance, but the system contains an internal secondary system of hard disks that backs up that data. If power is lost, internal batteries keep the unit powered until that backup operation is completed. When power is restored or the unit is turned back on, the system automatically copies data back on the RAM chips and operations resume. With our Cached Flash SSDs, the data is at rest in non-volatile flash memory. The DDR cache is battery-protected. In the event external power is lost, the system will use the internal batteries to run the system long enough to flush data from the DDR cache to the internal Flash memory RAID.

Chipkill Technology

Texas Memory Systems solid state disks are the only enterprise SSDs to implement Chipkill technology from IBM. Most solid state disks only implement limited ECC or other limited error-protecting code. With these systems, failure of a memory chip equals corrupted data. Chipkill is active on every memory board protecting data from single bit memory errors, multibit memory errors and entire chip failure.
Technically, Chipkill works hand-in-hand with the RamSan's ECC. Every bit in a memory "word" write is written on a different memory chip. Thus, a memory chip failure will cause a single bit correctable error across multiple memory words. The system's built-in ECC will easily correct these single bit errors. Further information on this technology is available at: http://www-05.ibm.com/hu/termekismertetok/xseries/dn/chipkill.pdf

Active Backup

Exclusive to TMS RAM based solid state disk systems is Active Backup™ software. Other SSDs and cache systems can only "destage" data from RAM to backup disks once power is already lost. This means that the system never backs up data during normal operation; therefore, the time-to-complete-backup after power loss may be unacceptably long. A RamSan with Active Backup continuously backs up data from RAM to the internal backup hard disks without affecting performance. This means in an emergency, data is anywhere from 60-100% on the backup hard drives already. Active Backup is currently available on RamSan-300, RamSan-400 and Tera-RamSan models.

Soft Error Correction

Exclusive to TMS solid state disk systems (RAM and Cached Flash) is Soft Error Correcting Firmware. Other SSDs implement ECC protection for their memory. The RamSan systems take this a step further. If a single bit memory error is detected in DDR memory, the RamSan systems will re-write the corrected data to the memory board and then re-read the data. If the data is corrected without ECC intervention when re-read, then an informational message is noted in the system logs. If the data still requires ECC intervention, then a warning message is noted in the system logs and communicated over SNMP so that the memory board can be monitored and potentially replaced. It is estimated that 90% of single bit errors are actually transient errors and are fixed with this Soft Error Correction firmware.

Triple Layer Flash Memory Protection

Layer 1: ECC for Flash Memory
A proprietary ECC implementation detects and corrects single bit errors and detects multi-bit errors for each 64 byte chunk of data. This error correction algorithm is far more aggressive than industry standard solutions that provide this level of protection across 512 byte chunks.
Layer 2: 64 Bit Word XOR for Flash Memory
In order to achieve high bandwidth operations and promote data quality, the RamSan-500 stripes data across nine Flash memory chips per write operation. Eight of these chips contain data and the ninth contains XOR data for the other eight chips. In the event that any particular chip is damaged, or a chip reports an uncorrected multi-bit error, the extra XOR chip allows the data to be completely recovered without resorting to rebuilding the RAID by simply rebuilding the data from the erroneous chip on the fly. When an event like this happens, the hardware will automatically remove the erroneous blocks from circulation by first performing a block rebuild that moves the data to a new location, then marks the particular block as bad and removes it from any addressing algorithms.
Layer 3: RAIDed Flash Memory Modules
The nine Flash memory modules each provide 128GB or 256GB (available) capacity. After RAID-5 is applied, the system presents either one or two terabytes of usable capacity. In the event a problem is observed with a Flash module the system continues to operate, the problem module can be hot swapped, and the RAID controller will rebuild the Flash array from the remaining modules.

Flash Wear Leveling

Wear leveling is a common feature in Flash SSD solutions. Wear leveling is required because the underlying Flash memory chips are specified to handle a limited number of writes. The RamSan-500 uses high quality SLC (single layer chip) NAND Flash memory. This memory is specified to handle 10x more programs/erases (writes) than the lower quality MLC (multi layer chip) NAND Flash used in inexpensive consumer devices. Despite the use of SLC Flash memory, it is still important to implement wear leveling strategies in order to prolong the write endurance of the system. The RamSan-500 includes algorithms to maximize its write life and is designed to operate for over four years even with a constant stream of writes.