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TM-66 DSP Chip
The TM-66 chip is the number crunching powerhouse in SAM DSP systems. Texas Memory Systems designed this chip to perform 32-bit IEEE floating-point arithmetic for use in heavy DSP solutions. The TM-66 has the required 1-Gflops of processing and the necessary I/O bandwidth of 1.2 GB/sec to process high-resolution algorithms effectively.  The TM-66 includes twelve floating-point adders, eight floating-point multipliers, 24 multi-port register files, six 32-bit data ports, and a 74-bit instruction port. The TM-66 chip is organized as two three-stage pipelines with separate register files between stages.  This pipeline architecture is very efficient for FFT, convolution, correlation, and matrix multiplication routines.
High Performance and I/O Bandwidth
While the TM-66 has a rating of 1-Gflops, it is still very efficient and easy to understand. We kept away from a complex internal cache memory scheme by including multiple high-speed data buses on the chip. Also, the TM-66 has a completely synchronous design. Data is pipelined through each execution unit on each clock edge. On each 50 MHz clock edge, four 32-bit data words are input, 20 floating point results are calculated, and two 32-bit data words are output. The programming, data flow, and processing are straightforward, thus it is easy to implement efficient algorithms.
Efficient Programming Architecture
The TM-66 uses a Very Long Instruction Word (VLIW) to control each resource within the chip in parallel. A separate instruction port (Harvard Architecture) keeps the instruction flow from conflicting with the massive data flow. This 74-bit instruction controls the 20 computational units, the 24 multi-port register files, and the on-chip data selectors on a cycle by cycle basis. Since external units provide the memory addressing and program counter control, the TM-66 chip is only concerned with blazing number crunching.

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